The present invention relates to the hardware and software architecture for input and output sub-systems as part of a multi-processor computer system including a number of central processing units (CPUs) and memory. Greater efficiency and speed is available through the use of a large numbers of CPUs capable of performing independent tasks of different jobs, or related jobs or related tasks of-a single job either simultaneously or with greater speed and efficiency than is possible with a smaller number of CPUs. The performance of such tasks will typically involve steps including accessing data and instructions from memory as well as accessing peripheral devices such as hard disk drives.
To efficiently complete tasks of different CPUs simultaneously, protocols must be developed and implemented to switch interconnections among the CPUs, memory, and peripheral devices. Such switching systems may be quite complex.
Moreover, with the use of a large number of CPUs and peripherals, the input and output system is potentially a speed-limiting aspect of the system. The input/output system must have sufficient uniformity and treatment of the various CPUs, the peripherals, and memory so that efficient interaction occurs, yet have sufficient customization for particular peripherals to communicate with such peripherals in the most efficient manner. As a result, it is desirable that an input/output system have sufficient uniformity to increase the efficiency of the interaction of the system subparts, yet have the circuitry necessary to vary the manner in which input and output is performed with peripherals.